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ISDB-T 1-Segment Tuner
S
T
A
R
T
DEVICE
ADDRESS
1100000
R/W
0
A
C
K
REGISTER
ADDRESS
00000000
A
C
K
S
T
A
R
T
DEVICE
ADDRESS
1100000
R/W
1
A
C
K
REG 00
DATA
xxxxxxxx
A
C
K
REG 01
DATA
xxxxxxxx
A
C
K
REG 02
DATA
xxxxxxxx
N
A
C
K
S
T
O
P
Figure 3. Receive Data from Read Registers
Applications Information
RF Input (UHFIN)
The MAX2163 UHFIN input is internally matched to
50 ? .
RF Gain Control (GC1)
The MAX2163 features multistage RF variable gain
amplifiers controlled by pin GC1 that provide in excess
of 54dB typical of RF gain control range. The voltage
control range is 0.3V at maximum gain to 2.1V at mini-
mum gain. The RF gain control can be configured for
open-loop control or for closed-loop RF automatic gain
control (AGC) when combined with the on-chip IF power
detector. To set the response time of the AGC, connect a
capacitor from GC1 to ground. See the Closed-Loop RF
Gain Control section for more information.
Optional RF Tracking Filter
The MAX2163 features an optional RF tracking filter at
the output of the 3rd-stage RFVGA. This filter is con-
trolled by the RFLT bits as shown in the MODE register.
See Table 7. To enable the filter, set RFFB bit to 0; to
disable filter, set RFFB bit to 1. See Table 17 for proper
center frequency settings. In the event that the RF track-
ing filter is not used, do not install the 18nH inductor.
Table 17. RFLT[2:0] Center Frequency
Settings
RF Overload Detector
The MAX2163 includes an RF overload detector. The
RF overload detector circuit is enabled or disabled with
the DRFD bit as shown in Table 10 (R-Divider LSB/CP
register).
IF Gain Control (GC2)
The MAX2163 features an IF variable gain amplifier that
provides in excess of 65dB of IF gain control range.
The voltage control VGC2 range is 0.3V at maximum
gain to 2.1V at minimum gain. The IF VGA is controlled
by the channel decoder.
IF Power Detector
The MAX2163 features a true RMS IF power detector at
the mixer output with adjustable bandwidth. The power
detector circuit is enabled or disabled with the
PDBM[1:0] bits in the PDET/RF-FILT register (Table 6).
The attack point can be set through the PDET[2:0] bits
in the PDET/RF-FILT register (see Table 6 for a summa-
ry of attack-point settings).
The PWRDET pin can be configured to provide a low-
impedance buffered and scaled version of either the
GC1 voltage when using the on-chip closed loop AGC,
or the IF power detectors RMS voltage for use in off-chip
closed loop AGC schemes. The output voltage at this pin
ranges from 0.3V to 2.1V, with 2.1V indicating the maxi-
mum RF input power. This output allows the baseband
processor to monitor the received RF power level.
RFLT
000
001
010
011
100
101
110
111
UHF (MHz)
470 –488
488 –512
512 –542
542 –572
572 –608
608 –656
656 –710
710 –806
When using the on-chip closed-loop AGC function
(PDBM = 11), the PWRDET buffer provides a low-
impedance buffered version of the GC1 voltage. This out-
put can be monitored by the demodulator LSI to determine
the state of the RF front-end and subsequently used to
control other circuits (external LNA) or various demodula-
tor functions. The PWRDET output can also be disabled
for reduced overall power consumption (PDBM = 00).
For use in off-chip closed-loop AGC schemes, the
PWRDET buffer output can be configured to provide a
low-impedance scaled version of the IF power detec-
tors RMS voltage (PDBM = 10). In this mode, an exter-
nal voltage is applied to the GC1 pin to close the loop.
______________________________________________________________________________________
19
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